Bumpless flip chip assembly with strips and via-fill

ABSTRACT

A flip chip assembly, and methods of making the same, including a substrate circuitry having a plurality of via apertures or holes, wherein preformed strips or wires hanging therein and filled conductive material together serve as the electrical connection between a semiconductor device and substrate circuitry. The method and device in accordance with the present invention may include attaching an integrated circuit (IC) chip to a rigid or flexible substrate circuitry having a plurality of pre-formed strips extending from patterned circuitry traces and hanging inside a plurality of through holes. These through holes are aligned and placed above the terminal pads so that the respective traces on the substrate can be readily connected to the respective input/output terminal pads of the IC chip through the leads inside the via apertures or holes. After attachment, an electrically conductive material, for example without limitation, adhesive or solder, is subsequently filled into the blind vias thereby connecting the leads-in-via to the terminal pads-in-via. The joining material not only provides the mechanical support but also the electrical continuity between IC chip and the circuitry of the substrate.

[0001] The present application is an application filed in accordancewith 35 U.S.C. §119 and claims the benefit of earlier filed Singaporeapplication number 9804796-2 filed on Dec. 17, 1998.

FIELD OF THE INVENTION

[0002] This invention relates generally to a semiconductor deviceassembly, and in particular, to a chip assembly which includes a singleor multi-layered substrate of which circuitry traces are connected tothe input/output terminal pads of the IC chip through deposition ofconductive material onto preformed leads and terminal pads inside thevia. The filled material includes electrical conductive adhesives andsolder.

BACKGROUND OF THE INVENTION

[0003] Recent developments of semiconductor packaging suggest anincreasingly critical role of the technology. New demands are comingfrom requirements for more leads per chip and hence smaller input/outputterminal pitch, shrinking die and package footprint, higher operationalfrequency that generate more heat, thus requiring advanced heatdissipation designs. All of these considerations must be met and, asusual, are placed in addition to the cost that packaging adds to thesemiconductor manufacturing food chain.

[0004] Conventionally, there are three predominant chip-level connectiontechnologies in use for integrated circuits, namely, wire bonding, tapeautomated bonding (TAB) and flip chip (FC), to electrically ormechanically connect integrated circuits to leadframe or substratecircuitry. Conventional flip chip technology is characterized asmounting of an un-packaged semiconductor chip with the active sidefacing down to a interconnect substrate through some kind of contactanchors such as solder, gold or organic conductive adhesive bumps. Themajor advantage of flip chip technology is the short interconnects,which, therefore, can handle high speed or high frequency signals. Thereare essentially no parasitic elements, such as inductance. Not only isthe signal propagation delay slashed, but much of the waveformdistortion is also eliminated. Flip Chip also allows an arrayinterconnecting layout that provides more I/O than a perimeterinterconnect with the same die size. Furthermore, it requires minimalmounting area and weight which results in overall cost saving since noextra packaging and less circuit board space is used. An example of sucha method is disclosed in U.S. Pat. No. 5,261,593 issued to Casson et al.

[0005] While flip chip technology shows tremendous advantage over wirebonding, its cost and technical limitations are significant. First ofall, prior art flip chip technology must confront the challenges offorming protruded contact anchors or bumps to serve as electricalconnections between integrated circuit chip and substrate circuitry.Examples of such an approach are disclosed in U.S. Pat No. 5,803,340issued to Yeh, et al. and U.S. Pat. No. 5,736,456 issued to Akram. Theytypically include a very costly vacuum process to deposit intermediateunder-bump layer that serves as adhesive and diffusion barrier. Thisbarrier layer is typically composed of a film stack that can be in thestructure of chromium/copper/gold. Bumping materials such as solder aresubsequently deposited onto this intermediate layer through evaporation,sputtering, electroplating, solder jetting or paste printing methodsfollowed by a reflow step to form the solder contacts.

[0006] Although evaporation and sputtering techniques can potentiallyoffer high density bumps, these processes need very tight control andnormally result in a poor yield. In addition, from the mechanicalstructure viewpoint, the coefficient off thermal expansion (CTE) ofsilicon and substrate may be quite different, the stress between thesetwo parts after attachment will build up and fully loaded on thesebumps. This will then cause severe joint cracking and disconnectionproblems during normal operation conditions. As a result, conventionalflip chip assembly is not only very costly but also suffers from a veryserious reliability problems and high fatality ratio.

[0007] Organic contacts, which utilize conductive adhesive to replacesolder, are also described in U.S. Pat. No. 5,627,405 issued to Chillaraand U.S. Pat. No. 5,611,140 issued to Kulesza, et. al. Generallyspeaking, the conductive adhesive which is made by adding conductivefillers to polymer binders holds a number of technical advantages suchas environmental compatible, lower temperature processing capability,fine pitch and simplified processes compared to soldering. However,these types of adhesives do not normally form the metallurgicalinterface in the classical sense. The basic electrical pathway isthrough conductive particles of the adhesives that are in contact withone another and reach out to the two contact surfaces of the components.

[0008] In view of the limitation of currently available integratedcircuits assembling methods, a high performance, reliable and economicalmethod that can effectively interconnect integrated circuits to theexternal circuitry would be greatly desirable.

SUMMARY OF THE INVENTION

[0009] It is therefore, an object of the present invention to provide aflip chip assembly to address high density, low cost and highperformance requirements of semiconductor packaging. It involves thebonding of substrate circuitry to semiconductor device through theconnection of preformed leads to the IC terminal pads inside the viaholes without the need for conventional bump, bonding wire, or othermedia. These unique joining approaches are capable of providing bothelectrical and mechanical connection between IC chip and circuitry ofthe substrate.

[0010] To achieve the foregoing and in accordance with the invention,the assembly includes a rigid or flexible dielectric substrate having aplurality of electrically conductive circuitry and a plurality of viaholes formed in the dielectric substrate. These conductive traces on thesurface of the substrate are extended into each specific via holesthrough the leads that are fabricated by conventional circuitrypatterning process, cutting or punching methods.

[0011] In one embodiment of the invention, the connection method maytake the form of solder paste printing, solder jetting or solderparticle placement. The most common solder system in use today istin-lead solder, although the invention is not limited to thisparticular type. For solder paste, a typical example of paste includes80% solder solids and 20% flux paste although this application is notlimited to this ratio. Solder paste, as stated, is applied in paste-likeform, preferably using a screening procedure known in the art. Aftersolder paste is dispensed onto the screen, a suitable squeegee typedevice is dragged across the screen, forcing the paste through the holesin the screen and into the substrate via holes. The screen is thenremoved, leaving the desired quantity of paste in each via.

[0012] According to a further aspect of the invention, the connectionmaterial may take the form of conductive adhesive to provide connectionof the IC terminal pads and pre-patterned leads of the substrate. Theconductive adhesive system holds a number of technical advantages suchas environmental compatibility, lower temperature processing capability,and simplified processes compared to soldering. Typically, theconductive adhesive system comprises a solution of polymerizablepre-cursor, fine metal particles and hardener, forming the paste. Thispaste can be filled into the blind vias through screen printing, stencilprinting or direct dispensing methods. After conductive adhesive pasteis filled in, the external energy such as heat or UV lights is appliedwhere the adhesive is cured and hardened thus providing an effectivemeans for electrical and mechanical contacts between circuitry leads andIC terminal pads. This is important in that it assures a very low costand environmentally friendly package. Its connection through metallizedvia wall in addition to the filled conductive material also assures animproved interface between substrate and chip due to a large contactarea.

[0013] A barrier layer over-coated on the aluminum terminal pad surfaceis preferred although for the copper terminal pad, it may not needfurther protection. This over coating is to provide pad surface forsolder wetting and to protect the connecting material against leaching,oxidation or degradation resulting from intermetallic formation duringexposure to soldering material and heat. This coating can beaccomplished by sputtering a stake of thin film thereon or by wetchemical plating technique such as electroless nickel and immersiongold.

[0014] The contacting leads that are located inside of the via holes maytake the form of strips with various shapes. A preferred fabricationprocess is by conventional photolithographic patterning and etchingprocesses. Alternately, they can be fabricated by micro-machining orlaser cutting. After these leads are formed, they are bent towardsinside of the via holes in order to provide an effective connection pathbetween IC pads and the circuitry. The bending of the leads can beachieved by a variety of methods such as vacuum suction, air blowing ormechanical pushing.

[0015] The via holes of the substrate circuitry can be formed by varioustechniques including mechanical drilling, punching, plasma etching, orlaser drilling. They can be formed before or after copper laminationdepends on the substrate manufacturing process. These via holes areformed at the locations where electrical circuitry on one side of thesubstrate can be connected to the opposite side of the surface on whichthe semiconductor chip or chips are mounted and their input/outputterminal pads can be exposed through these holes.

[0016] Using extended leads and conductive material directly depositedin via hole can effectively connect the IC chip and dielectric substratecircuitry without external bumps or wires. This approach allows highlyreliable, low profile, high performance and low cost assembly to beachieved. In particular, a small via hole which can be formed by laseror other techniques allows very fine pitch terminal pad to beinterconnected, can significantly enhance the capability of packagingfuture high I/O semiconductor chips.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 is a fragmented partial sectional perspective view of asubstrate showing via hole and traces of the substrate circuitry of thepresent invention.

[0018]FIGS. 2A - 2E are fragmented partial sectional side eleveationalviews showing sequentially the method of dispensing conductive adhesivesin the via holes according to the present invention.

[0019]FIGS. 3A - 3F are fragmented partial sectional side elevationalviews showing sequentially the method of solder paste printing into thevia followed by re-flowing process according to another embodiment ofthe invention.

DETAILED DESCRIPTION OF THE INVENTION

[0020] According to the invention, a flip chip assembly is provided toaddress high density, low cost and high performance requirements ofsemiconductor packaging. It involves the bonding of substrate circuitryto semiconductor device through the connection of pre-formed leads tothe IC terminal pads inside the via holes without the need forconventional bump, bonding wire, or other media. These unique joiningapproaches are capable of providing both electrical and mechanicalconnection between IC chip and circuitry of the substrate.

[0021] To achieve the foregoing and in accordance with the invention,the assembly includes a rigid or flexible dielectric substrate having aplurality of electrically conductive circuitry and a plurality of viaholes formed in the dielectric substrate. These conductive traces on thesurface of the substrate are extended into each specific via holesthrough the leads that are fabricated by conventional circuitrypatterning process, cutting or punching methods. FIG. 1 is an isometricview of a section of such a substrate 101 on which vias 102 are normallyformed by laser or mechanical drilling. These via holes 102 are to serveas the interconnecting channels between circuitry traces 103 and ICterminal pads through the preformed leads 104 hanging inside the vias.Circuitry traces 103, which extend from vias 102 along an outer surfaceof the substrate will lead to another pad connection or next levelassembly.

[0022] The orientation of the contact ensures that at least one of thevia holes in the dielectric substrate are aligned to the pads of the ICchip so that these pads can be totally or partially exposed through theopposite side of the substrate. After alignment, the IC chip is attachedto the dielectric substrate through adhesive film or paste, ormechanical techniques thus form an assembly. Electrically conductivematerial is subsequently filled into the via holes to connect theseleads as well as the input/output pads of the IC chip. These filledconductive materials in the via hole can provide electrical andmechanical connections between the chip and the traces of the dielectriccircuitry. After substrate circuitry is connected to the terminal pad,the mechanical and chemical means used to attach the chip and substratecan be removed. In the alternative, it can be left in as an integralpart of the assembly since this attachment can also provide mechanicalsupport.

[0023] As defined herein, the preferred embodiment is particularlydirected to the bonding of an integrated circuit (IC) chip to a flexiblecircuitized substrate, or to a more rigid, circuitized substrate, aparticular example of the later being a printed circuit board. It is tobe understood, however, that the invention is not limited to attachmentto printed circuit boards, in that other circuitized substrates,including known flexible substrate tapes or ceramic substrates, may beemployed. In general, organic-type substrate is preferable for thepurpose of lower cost, superior dielectric property whereasinorganic-type of substrate is preferable when high thermal dissipationand matched coefficient of expansion are desired. By the term“substrate” as used herein is meant to define as at least one layer ofthe dielectric material having at least one conductive layer thereon.Printed circuit boards of similar type are well known in the electronicindustry, as well as the processes for making same, and therefore,further definition is not believed to be necessary. Such structures mayinclude many more electrically conductive layers than those depicted inFIGS. 1 through 3, depending on the desired operational characteristics.As is known, such electrically conductive layers may function as signal,power, and/or ground layers.

[0024] In one embodiment of the invention, the connection method maytake the form of solder paste printing, solder jetting or solderparticle placement. The most common solder system in use today istin-lead solder, although the invention is not limited to thisparticular type. For solder paste, a typical example of paste includes80% solder solids and 20% flux paste although this application is notlimited to this ratio. Solder paste, as stated, is applied in paste-likeform, preferably using a screening procedure known in the art. Aftersolder paste is dispensed onto the screen, forcing the paste through theholes in the screen and into the substrate via holes. The screen is thenremoved, leaving the desired quantity of paste in each via.

[0025] It should be understood from the teaching herein that theparticular solder paste and methods of dispensing depicted above is notmeant to limit the invention, in that it is also possible to placesolder paste by stencil printing, direct dispensing or other method.Heat, to a predetermined temperature sufficient to cause solder paste to“ball up”, is then applied to the assembly, at least in the vicinity ofthe via holes. A preferred application of such heat is achieved by usinglaser. Alternatively, the attached assembly may be placed in a suitableoven to effect solder re-flow and bonding to the IC terminals as well asthe extended leads which are inside of the via holes. One example ofsuch an approach is an infrared (IR) continuous belt re-flow oven. Asyet another alternative, hot nitrogen gas may be directed onto thesolder member. This re-flow formation results in solder structure, whichwill electrically and physically interconnect the leads and pads foreventual permanent connection thereto. This is important in that it notonly assures a wide selection of the solder system but also assures avery low stress and therefore reliable connection between substrate andchip due to the flexibility of the strips.

[0026] According to a further aspect of the invention, the-connectionmaterial may take the form of conductive adhesive to provide connectionof the IC terminal pads and pre-patterned leads of the substrate. Theconductive adhesive system holds a number of technical advantages suchas environmental compatibility, lower temperature processing capability,and simplified processes compared to soldering. Typically, theconductive adhesive system comprises a solution of polymerizablepre-cursor, fine metal particles and hardener, forming the paste. Thispaste can be filled into the blind vias through screen printing, stencilprinting or direct dispensing methods. After conductive adhesive pasteis filled in, the external energy such as heat or UV lights is appliedwhere the adhesive is cured and hardened thus providing an effectivemeans for electrical and mechanical contacts between circuitry leads andIC terminal pads. This is important in that it assures a very low costand environmentally friendly package. Its connection through metallizedvia wall in addition to the filled conductive material also assures animproved interface between substrate and chip due to a large contactarea.

[0027] A barrier layer over-coated on the aluminum terminal pad surfaceis preferred although for the copper terminal pad, it may not needfurther protection. This over coating is to provide pad surface forsolder wetting and to protect the connecting material against leaching,oxidation or degradation resulting from intermetallic formation duringexposure to soldering material and heat. This coating can beaccomplished by sputtering a stake of thin film thereon or by wetchemical plating technique such as electroless nickel and immersiongold.

[0028] According to the invention, the contacting leads that are locatedinside of the via holes may take the form of strips with various shapes.A preferred fabrication process is by conventional photolithographicpatterning and etching processes. Alternately, they can be fabricated bymicromachining or laser cutting. After these leads are formed, they arebent toward inside of the via holes in order to provide an effectiveconnection path between IC pads and the circuitry. The bending of theleads can be achieved by a variety of methods such as vacuum suction,air blowing or mechanical pushing.

[0029] According to the invention, via holes of the substrate circuitrycan be formed by various techniques including mechanical drilling,punching, plasma etching or laser drilling. They can be formed before orafter copper lamination depends on the substrate manufacturing process.These via holes are formed at the locations where electrical circuitryon one side of the substrate can be connected to the opposite side ofthe surface on which the semiconductor chip or chips are mounted andtheir input/output terminal pads can be exposed through these holes.

[0030] If the finished product is, for instance, a ball grid arraypackage (BGA), solder balls will normally be placed on the specific padson the surface of the dielectric substrate. This finished package can beconnected to a printed circuit board by reflowing the solder balls toform an attachment to the traces of the printed circuit board.

[0031] Using extended leads and conductive material directly depositedin via hole can effectively connect the IC chip and dielectric substratecircuitry without external bumps or wires. This approach allows highlyreliable, low profile, high performance and low cost assembly to beachieved. In particular, a small via hole, which can be formed by laseror other techniques allows very fine pitch terminal pad to beinterconnected, can significantly enhance the capability of packagingfuture high I/O semiconductor chips.

[0032] The present invention will be illustrated further by thefollowing examples. These examples are meant to illustrate and not tolimit the invention, the scope of which is defined solely by theappended claims.

EXAMPLES 1

[0033]FIG. 2A shows an integrated circuit chip 201 with various types oftransistor, wiring and the like (not shown) which has a plurality ofexposed input/output terminal pads 202 (only one shown). These pads 202were firstly cleaned by dipping the integrated circuitry chip 201 in aphosphoric acid solution at room temperature with an immersion time of10 minutes to remove the surface oxide film. This chip was next dippedin a diluted catalytic solution Enthone “Alumon EN” at 25 degree C. for20 seconds to form a thin zinc film (not shown) on the surface ofaluminum allow terminals 202. Following steps include a thoroughdistillated water rinse and electroless plating using Shipley “NIPOSIT468” at 85 degree C. The electroless plating will continuously deposit athin layer of nickel film 203 containing phosphorous (to be referred toas a nickel film hereafter) on the input/output terminal pads 202 of theintegrated circuits chips 201.

[0034]FIG. 2B shows a cross sectional view of the dielectric substrate204 having a plurality of circuitry traces 205 partially covered by thesolder mask 206. These circuitry traces 205 extended to via hole 207 andsplit into a plurality of leads 208 which are bent toward inside of thevia holes. The holes 207 are formed in such a manner that the terminalpads 202 of the integrated circuit chip 201 can be totally or partiallyexposed when integrated circuit chip 201 is mounted on the substrate204. The leads 208 are bent toward the terminal pad and serve as theelectrically connecting channels for respective traces 205 of thesubstrate 204 with respective terminal pads 202 of the integratedcircuit chips 201 of FIG. 2A.

[0035] As shown in FIG. 2C, the substrate 204 is next securely attachedto the IC chip 201 by the adhesive paste ABLESTIK “ABLEBOND 961-2” 209.

[0036] As shown in FIG. 2D, the electrical conductive paste Solder-Sub“ME 8659-SMT” 210 is filled into the via holes. The filled conductiveepoxy is cured at 150 degree Celsius for 5 minutes to harden whichincreases the bonding strength between circuitry leads and IC terminalpads. These joints will provide an effective means for electrical andmechanical connections between the input/output terminals and the tracesof the dielectric circuitry, thereby completing the fabrication of theelectrical bonding interconnect.

[0037] As shown in FIG. 2E, the solder ball 211 is attached to theconnection pad of the substrate circuitry and the package is ready forthe next level assembly.

EXAMPLE 2

[0038] Referring now to FIG. 3A, an integrated circuit (IC) chip 301similar to that in example 1 was cleaned in an alkaline solutioncontaining 0.05M phosphoric acid at room temperature (25 degree Celsius)with immersion time of 1 minute. The chip was then thoroughly rinsed indistillated water to ensure there is no residue on the surface of ICchip. A stake of thin film 303 in the structure of chromium (500A)/copper (700 Angstroms)/gold (1000 Angstroms) was deposited andpatterned on the terminal pads 302 to serve as the barrier and adhesivelayer.

[0039]FIG. 3B shows a dielectric substrate 304 having a plurality ofelectrically conductive circuitry traces 305 partially covered by thesolder mask 306. These traces 305 on the substrate extend into the viaholes 307 and split into a plurality of leads 308 which are bent towardinside of the via holes 307. The holes 307 are formed in such a mannerthat the terminal pads 302 (FIG. 3A) of the integrated circuit chip 301(FIG. 3A) can be totally or partially exposed when integrated circuitchip 301 (FIG. 3A) is mounted on the substrate 304. The bent leads 308are to serve as the electrically connecting channels for respectivetraces 305 of the substrate 304 with respective terminal pads 302 (FIG.3A) of the integrated circuit chips 301 (FIG. 3A).

[0040] As shown in FIG. 3C, the IC chip 301 is next securely attached tothe substrate circuitry 304 by an adhesive film ABLESTIK “ABLEFILM 562K”309.

[0041] As show in FIG. 3D, the solder paste KESTER SOLDER “R253” 310 isnext screen printed into the via hole.

[0042] As shown in FIG. 3E, the assembly is next re-flowed at the peaktemperature ranging from 210 to 215 degree of Celsius. After the re-flowprocess, the assembly is cooled down at the rate of 1 degree of Celsiusper second using ambient air to solidify the solder therein. Thisre-flow process enables the filled solder firmly connect the leadsinside the vias as well as the terminal pads at the bottom of the vias.

[0043] As shown in FIG. 3F, the solder ball 311 is next attached to theconnection pad of the substrate circuitry and the package is ready forthe next level assembly.

[0044] Though only one solder systems is shown in the figure, it is tobe understood that many solder systems, can also be applied and servethe connection purpose.

[0045] The present invention may be embodied in other specific formswithout departing from the spirit or essential characteristics thereof.The presently disclosed embodiments are, therefore, to be considered inall respects as illustrative and not restrictive, the scope of theinvention being indicated by the appended claims and all changes whichcome within the meaning and range of equivalency of the claims are,therefore, to be embraced therein.

What is claimed is:
 1. A flip chip assembly, comprising: (a) adielectric substrate having a plurality of via apertures; (b) saiddielectric substrate having a first and second opposite surfaces and aplurality of electrically conductive traces being formed on the firstsurface of said dielectric substrate, said traces extending intospecific via apertures through at least one lead but preferable aplurality of leads, wherein the leads are formed on the top of and bentinto said via apertures; (c) a semiconductor device having a firstsurface and a plurality of input/output terminal pads with a stack ofmetal film deposited thereon; (d) said substrate being attached to saidsemiconductor device on the second surface of said substrate, andwherein the via apertures of said substrate align with said terminalpads such that at least one of said terminal pads can be at leastpartially exposed through said via apertures from said first surface ofthe said substrate; and (e) an electrical continuity between saidsubstrate and said semiconductor device is provided by depositingelectrically conductive material in said vias which connect the bentleads and the terminal pads.
 2. The flip chip as recited in claim 1 ,wherein a dielectric material of said substrate is made of plastic. 3.The flip chip as recited in claim 1 , wherein a dielectric material ofsaid substrate is a flexible film.
 4. The flip chip as recited in claim1 , wherein a dielectric material of said substrate is made of ceramics.5. The flip chip as recited in claim 1 , wherein said via apertures areformed by laser drilling.
 6. The flip chip as recited in claim 1 ,wherein said via apertures are formed by mechanical punching.
 7. Theflip chip as recited in claim 1 , wherein said via apertures are formedby plasma etching.
 8. The flip chip as recited in claim 1 , wherein saidvia apertures are formed by chemical etching.
 9. The flip chip asrecited in claim 1 , wherein said electrical leads are fabricated byphoto lithographic and etching processes.
 10. The flip chip as recitedin claim 1 , wherein said electrical leads are fabricated by lasercutting.
 11. The flip chip as recited in claim 1 , wherein said stack ofmetal film is deposited by sputtering process.
 12. The flip chip asrecited in claim 1 , wherein said stack of metal film is deposited byevaporation process.
 13. The flip chip as recited in claim 1 , whereinsaid stack of metal film is deposited by electroless plating process.14. The flip chip as recited in claim 1 , wherein said semiconductordevice is attached to said dielectric substrate with adhesive paste. 15.The flip chip as recited in claim 1 , wherein said semiconductor deviceis attached to said dielectric substrate with adhesive film.
 16. Theflip chip as recited in claim 1 , wherein said electrically conductivematerial is a conductive adhesive.
 17. The flip chip as recited in claim1 , wherein the electrically conductive material is an intrinsicconductive polymer.
 18. The flip chip as recited in claim 1 , whereinthe electrically conductive material is solder.
 19. The flip chip asrecited in claim 1 , wherein the deposition method is screen printing.20. The flip chip as recited in claim 1 , wherein the deposition methodis dispensing.
 21. The flip chip as recited in claim 1 , wherein thedeposition method is jetting.